Multi-phase clock generators are widely used in both analogue and digital circuits, especially in high-speed and high-performance digital circuits. Conventionally, locked phase technology is used for generating multi-phase clock signals. Locked phase technology, adapted for automatic phase control, has been developed for 100 years and widely used in electronic systems like communications, navigations, radars, computers and domestic appliances. In general, a Phase Locked Loop (PLL) is used to implement the phase control. In some occasions, the PLL may be replaced by a Delay Locked Loop (DLL) in which a voltage controlled oscillator originally configured in the PLL is removed, while a Voltage Controlled Delay Line (VCDL) may be used for delaying an input clock signal for several cycles and then outputting the delayed clock signal. Therefore, synchronization between the input and the output signals can be achieved. For the PLL, as a voltage controlled oscillator is used, which is very sensitive to interference and noise from the power supply or substrate, it may have unacceptable stability and shake resistance.
Currently, for outputting clock signals with high performance, generally a DLL is applied. A DLL can generate and output a multi-phase clock with the same frequency as the reference signal, after the locking. The multi-phase clock can be used to eliminate clock delay, or being transferred into a high-frequency clock or a low-frequency clock through a frequency multiplier or a frequency divider. FIG. 1 schematically illustrates the structure of an existing DLL. The DLL includes a phase detector (PD) 101, a charge pump (CP) and loop filter (LPF) 102, and a VCDL 103. The PD 101 is used for detecting phases of an input signal Fin and an output signal Fout, and then outputting a corresponding detection signal VPD, which indicates to upraise or lower down the signal phase. Under control of the detection signal VPD, the charge pump performs a charging or discharging operation, which eventually becomes a control voltage VCTRL through the LPF. The control voltage VCTRL then comes to the VCDL 103 which includes a plurality of multi-level delay units connected in series. The input signal Fin is inputted to the VCDL 103, delayed by the multi-level delay units, and outputted by the VCDL 103 as the output signal Fout. During the above process, the voltage VCTRL can adjust the delay periods of the multi-level delay units of the VCDL 103. Further, by using the negative feedback control through the whole loop, the phase difference between the input signal Fin and the output signal Fout after the locking can be maintained as one cycle.
DLL has advantages like smaller jitters and less noise. However, due to the usage of the charge pump, phase noise is inevitable.